In a semiconductor test system, a driver circuit is provided for each test pin of a device under test to supply the test signal with variable slew rates and voltage levels to the test pin. Typically, the driver circuit receives an input test signal and high and low reference voltages and generates an output test signal having the voltage levels defined by the reference voltages.
A prior art driver circuit is shown in FIG. 11. The driver circuit in FIG. 11 is designed to drive the input pins of a device to be tested. As this driver circuit is divided into a switching-circuit section 611 and output buffer section 612, there are various circuit stages. Furthermore, there is always current flowing in each circuit section. In addition, output current from this driver circuit always flows as an output idling current, even in the steady state. For this reason the circuit of FIG. 11 is limited in its ability to satisfy specifications required for handling high amplitudes and high speeds while achieving low power consumption.
Another example of the prior art is a two-branch driver circuit formed on a monolithic IC. This circuit is explained by referring to FIGS. 8, 9 and 10. The two-branch driver circuit is used where multiple devices are tested simultaneously in a semiconductor test system. It supplies the desired amplitude to the input pins of two devices (DUT) to be tested by receiving one test-pattern signal.
The circuit comprises a level-conversion circuit 200, first driver circuit 300, and second driver circuit 350. Here, the first driver circuit 300 and second driver circuit 350 are identical. The operation of the level conversion circuit 200 is described below:
The level-conversion circuit 200 supplies a voltage signal DR to the two-driver circuit in response to the conditions of 1) differential pattern signals PAT and NPAT, 2) an analog voltage signal VH that determines the high-level voltage of the driver output, 3) an analog voltage signal VL that determines the low-level voltage, 4) an analog control signal TRC that determines the rise time, and 5) an analog control signal TFC that determines the fall time.
The level-conversion circuit 200 comprises level-shift section 220, constant-current sections 201 and 203, switching sections 202 and 204, and diode bridges (DB) 231 and 232 as shown in FIG. 9.
A power supply VCCA1 is a positive power supply, for example, +11 V. In addition, a power supply VEEA 1 is a negative power supply, for example, -6 V.
After receiving the differential signal PAT and NPAT at the ECL level, the level-shift section 220 outputs differential signals Henb1, Lenb1, Henb2, and Lenb2 which are level-converted to the switch section 202 on the positive power-supply side and the switch section 204 on the negative power-supply side in order to switch DB231 and DB232. This internal circuit and its operation are described later on.
The switch section 202 and switch section 204 comprise a complementary circuit, and operating both sections switches either DB231 or DB232 and outputs analog voltages VH or VL to the output terminal DR.
When the differential switching signals Henb1 and Lenb1 are received from the level-shift section 220, and when Henb1 &lt;Lenb1, PNP transistor Q283 side becomes conductive, the switch section 202 supplies current i91, which biases DB231 in the forward direction. Conversely, when Henb1&gt;Lenb1, the Q284 side of PNP transistor becomes conductive and supplies current i92, which biases DB232 in the forward direction. The value of the bias current i91 is determined by either the relationship between resistor R274 on the switching section 202 side, voltage Henb1 and VCCA1, or the relationship between resistor R275 on the switching section 204 side, voltage Henb2 and VEEA1.
When Henb2&gt;Lenb2, PNP transistor Q205 becomes conductive, the switch section 204 sinks current i91 from DB231, and switches on DB232 along with the said Q283. Conversely, when Henb1&lt;Lenb1, the NPN transistor Q206 becomes conductive and switches on DB232 along with the said Q284. As a result, either DB231 or DB232 are switched on.
The analog voltage signal VH or VL is a constant analog voltage that determines a high level or low level of the driver output terminal out1, for example, voltage applied to the input pins of TTL- and ECL-compatible devices.
DB231 and DB232 produce output by switching either the analog voltage signal VH or VL. These devices for high-speed analog switches by building a bridge connecting eight diodes. The analog-voltage signal VH is supplied to the output terminal DR for DB232 while the analog-voltage signal VL is supplied to the output terminal DR for DB232.
More particularly, when bias current in the forward direction flows into the upper and lower two terminals of the diode bridge DB231 or DB232 as shown in FIG. 9, the state across the left-right terminals becomes an equivalent on stage, whereas when the bias current is absent it becomes an off stage. Hence, VH and VL analog signals can be switched at high speeds without being affected by the voltage on the bias-current side by using the composition of constant-current circuits of the switching sections 202 and 204.
Diodes used for this purpose can be a Schottky diode or a diode formed by connecting the base and collector of a transistor. Generally, when forming diodes on a monolithic structure, it is desirable to form a diode using a transistor because the area of the chip can be reduced. Furthermore, the Schottky diode has an advantage with respect to the reversed breakdown voltage, and it may be used separately or in combination depending on power-supply voltages, etc.
When DB231 and DB232 are in an off stage and a potential across the upper and lower terminals of these devices is in an indeterminate state, the high-speed switching operation of the constant-current sections 201 and 203 can be troublesome during the next switching transition. For this reason it is intended to make the potential anything other than an indeterminate state by applying extremely small current.
The circuit operation of the level-shift section 220 is described below.
The circuit composition of the level-shift section 220 is a bias-voltage supply section 221, differential amplifiers 222 and 224, and differential-current control sections 223 and 225 as shown in FIG. 10.
Differential voltages PAT and NPAT at the ECL level are input to the two differential amplifiers 222 and 224. First, the PAT and NPAT signals are input to the bases of Q10 and Q11 of the differential amplifier section 222 of NPN transistor, and differential switching signals Henb1 and Lenb1, which are shifted to a positive voltage level on the collector side are output. The differential current control section 223 is connected on the emitter side of the differential amplifier section 222.
This differential-current amplifier section 223 receives a constant voltage from the bias-voltage supply section 221 and forms a constant-current circuit with transmitter Q12, and resistors R9 and R8. In addition, the constant current can be made variable by altering the external voltage signal TRC through R8. In this way, output amplitudes of the switching signals Henb1 and Lenb1 can be variable and the transition time of a waveform on the rising side of the output signal out1 output by the driver circuit can be controlled continuously.
Secondly, the PAT and NPAT signals are input to the bases of Q14 and Q15 of the differential-amplifier section 224 of NPN transistor. Output differential-switching signals Henb2 and Lenb2 are thereby shifted to a negative-voltage level on the collector side. A differential-current control section 225 is connected on the emitter side of the differential-amplifier section 224, and similar to the above description, the constant current can be made variable by altering the external voltage signal TFC through R10. In this way, the transition time of a waveform on the rising side of the output signal out1 can be controlled continuously.
The operation of the first driver circuit 300 is described by referring to FIG. 8.
The first driver circuit 300 is composed of constant-current sources 311 and 312, PNP transistors Q381 and Q384, NPN transistors Q382 and Q383, diodes D391 and D392, and resistors R386 and R387. In this circuit, circuit elements not directly related to power consumption are omitted.
A power supply VCCA2 is a positive power supply similar to the power supply VCCA1, and a power supply VEEA 2 too is a negative power supply similar to the power supply VEEA1.
The driver circuit 300 receives the analog voltage signal DR of VH/VL amplitudes described in the above level-conversion circuit 200, and it is a high-speed analog buffer circuit that supplies maximum load current of +/- Imax by converting to a low impedance of less than 50 ohms. Because it either supplies a source current to the load or forces a sink current from the load side to flow in, it is composed of a complementary circuit. In addition, an overshoot/undershoot voltage waveform caused by a reflection from the load side needs to be absorbed.
For this reason both the complementary transistors Q383 and Q384 in the output stage are always biased to the A-class operation state. Hence, both the transistors always drive the maximum load current Imax, even when external input and output currents are absent. A potential difference across resistors R386 and R387 is always constant, and the potential is given by a voltage determined by the potential difference of diodes D391 or D392.
The constant-current sources 311 and 312 flow at a constant current such that at least transistors Q383 and Q384 can drive the maximum load current Imax.
The analog voltage signal DR is input to the corresponding bases of Q383 and Q384 after being input to the bases of Q381 and Q382, emitter-followered, and providing the offset of the voltage of diodes D391 and D392. Here, since a potential difference between the bases of Q383 and Q384 is provided by a fixed-potential difference by using two diodes and two voltage Vbe, the output-stage transistor always performs the A-class operation. Thus, an output voltage corresponding to the input analog voltage signal DR is output.
As explained above, in the circuit configuration of the driver circuit, both the output stage transistors Q383 and Q384 are required to provide the maximum load current Imax all the time. Hence, the driver circuit 300 always consumes the maximum power regardless of the loading condition, and has a limitation in terms of reducing power consumption without degrading the switching speeds.
For this reason, a semiconductor test system that uses hundreds of channels with this driver circuit, requires cooling system that becomes bulky. Furthermore, such a system is subject to a limitation of high-density implementation, or a power supply with a large capacity is required, which leads to a large test system. Hence, this type of system is undesirable. Furthermore, the power-consumption reduction is limited by this circuit method.
There were such disadvantages with this type of system that it required a ceramic package as a container housing a monolithic IC, which had high radiation ability and was expensive, and this system was difficult to house in an inexpensive plastic package.
As another example of the prior art technology, a driver circuit with the driver-inhibit ability is shown in FIG. 12.
As shown in FIG. 12, the driver-inhibit circuit is arranged on the VH and VL sides. The VH side is explained first, but the VL side operates in the same manner.
Normally, the clamp voltage Pclmp 651 is set to a higher voltage than the maximum driver voltage set to VH 603. For this reason, diode 751 is in a cut-off state during ordinary driver output. The base voltage VA of transistor 702 becomes a value that is the sum of a voltage across the base-emitter of transistor 701 and a voltage in the forward direction of diode 901 subtracted from the VH. As a result, the driver output 615 becomes the VH.
A DRE 2 signal 682 is set to logic "1" during the driver-inhibit operation. Hence, a base current of transistor 702 is supplied from the power voltage PV 621 through transistors 854 and 855. Diodes 751 and 764 are turned on and the base-potential VA of transistor 702 reaches the clamp voltage Pclmp 651. Hence, transistor 702 is cut off.
At the same time, the high-level setting signal DH1 is set to logic "0." As a result, transistor 708 is also cut off. Similarly, as transistor 802 and 803, too, are cut off on the VL side, the driver output 615 becomes a high-impedance state.
The time chart of the third embodiment of this invention is illustrated in FIG. 4. As shown in FIG. 4a, the driver changes from an on period to an off period, i.e. the driver-inhibit period, then it changes back to an on period.
The voltage VA, as shown in FIG. 4b, varies from the driver voltage VH to the clamp voltage Pclmp, and this amplitude is relatively large. Hence, its transition time is not negligible. Especially, it is important when the driver changes from the inhibit state to an on state. That is, as shown in FIG. 4e, it would take time Ton for the base voltage VA of transistor 702 to change from the clamp voltage to the VH potential. On the other hand, when the high-level setting signal DH1 of the driver is set to logic "1," a voltage across resistor 709 is dropped immediately through transistor 704, as a result transistor 703 is turned on immediately. By this event transistor 702 is turned on, and the base-voltage VA appears at the driver output 615 as it is.
Therefore, as shown in FIG. 4a, a transition voltage due to the transistor switching to an on state is outputted to the driver output 616 as a spike waveform, and this spike is maintained as an I/O spike during a period of Ton.
In this way, the longer the transition period, the greater the I/O spike width and amplitude. This has an undesirable effect on DUT.